Computing for Diagnosis of HDL Code
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-54825-8_7
Reference18 articles.
1. Bergeron, J. (2006). Writing Testbenches Using SystemVerilog. Springer. New York.
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3. Benabboud, Y., Bosio, A., Girard, P., Pravossoudovitch, S., Virazel, A., Bouzaida, L., & Izaute, I. (2009). A case study on logic diagnosis for system-on-chip. In International symposium on quality electronic design, 2009.
4. Ubar, R., Kostin, S., & Raik, J. (2009). Block-level fault model-free debug and diagnosis in digital systems. In DSD ‘09, 12th Euromicro conference, 2009.
5. Sohofi, H., & Navabi, Z. (2014). Assertion-based verification for system-level designs. In 15th international symposium on quality electronic design (ISQED), 2014.
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