Scheduling for Better Energy Efficiency on Many-Core Chips-Reference-Cited by-同舟云学术

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Scheduling for Better Energy Efficiency on Many-Core Chips

Published:2017 Issue: Volume: Page:46-68
ISSN:0302-9743
Container-title:Job Scheduling Strategies for Parallel Processing
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Author:

Kang Chanseok,Lee Seungyul,Lee Yong-Jun,Lee Jaejin,Egger Bernhard

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-61756-5_3

Reference22 articles.

1. Agerwala, T., Chatterjee, S.: Computer architecture: Challenges and opportunities for the next decade. IEEE Micro 25(3), 58–69 (2005)

2. Barroso, L.A., Gharachorloo, K., McNamara, R., Nowatzyk, A., Qadeer, S., Sano, B., Smith, S., Stets, R., Verghese, B.: Piranha: a scalable architecture based on single-chip multiprocessing. In: Proceedings of the 27th Annual International Symposium on Computer Architecture, ISCA 2000, pp. 282–293. ACM, New York (2000)

3. Borkar, S.: Thousand core chips-a technology perspective. In: Proceedings of the 44th Annual Design Automation Conference, DAC 2007, pp. 746–749. ACM, New York (2007)

4. Burd, T.D., Brodersen, R.W.: Energy efficient CMOS microprocessor design. In: Proceedings of the Twenty-Eighth Hawaii International Conference on System Sciences, vol. 1, pp. 288–297 (1995)

5. Cai, Q., González, J., Magklis, G., Chaparro, P., González, A.: Thread shuffling: combining DVFS and thread migration to reduce energy consumptions for multi-core systems. In: Proceedings of the 17th IEEE/ACM International Symposium on Low-power Electronics and Design, ISLPED 2011, pp. 379–384. IEEE Press, Piscataway (2011)

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1. POSTER: NUMA-Aware Power Management for Chip Multiprocessors;2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT);2017-09

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