Extracting of High-Level Structural Representation from VLSI Circuit Description Using Tangled Logic Structures-Reference-Cited by-同舟云学术

Extracting of High-Level Structural Representation from VLSI Circuit Description Using Tangled Logic Structures

Published:2017-07-26 Issue: Volume: Page:318-323
ISSN:2194-5357
Container-title:Advances in Intelligent Systems and Computing
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Author:

Trukhachev Andrey,Ivanova Natalia

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-63940-6_45

Reference12 articles.

1. Lester, A., Bazargan-Sabet, P.: YAGLE, a second generation functional abstractor for CMOS VLSI circuits. In: Proceedings of the Tenth International Conference on Microelectronics, pp. 265–268 (1998)

2. Pelz, G., Roettcher, U.: Pattern matching and refinement hybrid approach to circuit comparison. IEEE Trans. Comput.-Aided Des. 13, 264–275 (1994)

3. Graeb, H., Zizala, S.: The sizing rules method for analog integrated circuit design. In: Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, pp. 343–349 (2001)

4. Huang, K.-T., Overhauser, D.: A novel graph algorithm for circuit recognition. In: Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1695–1698 (1995)

5. Zhang, K., Du, H.: Maximizing influence in a social network: improved results using a genetic algorithm. Phys. A Stat. Mech. Appl. 478, 20–30 (2017)

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