1. Y.-C. Chang, Y.-W. Chang, G.-M. Wu, S.-W. Wu, B*-trees: A new representation for nonslicing floorplans, in Proceedings of the 37th ACM/IEEE Design Automation Conference (DAC), 2000, pp. 458–463
2. A. Canelas, R. Martins, R. Póvoa, N. Lourenço, J. Guilherme, N. Horta, Enhancing an automatic analog IC design flow by using a technology-independent module generator, in Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, ed. by M. Fakhfakh, E. Tlelo-Cuautle, M.H. Fino (IGI Global, Hershey, PA, 2014)
3. F. Balasa, S.C. Maruvada, K. Krishnamoorthy, Using red-black interval trees in device-level analog placement with symmetry constraints, in Proceedings of the Asian and South Pacific—Design Automation Conference (ASP-DAC), Jan 2003, pp. 777–782
4. T. Carusone, D. Johns, K. Martin, Analog Integrated Circuit Design, 2nd edn. (Wiley, New York, 2011)
5. Y. Yilmaz, G. Dundar, Analog layout generator for CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 28(1), 32–45 (2009)