Parallel FDFM Approach for Computing GCDs Using the FPGA

Author:

Zhou Xin,Nakano Koji,Ito Yasuaki

Publisher

Springer International Publishing

Reference19 articles.

1. Ago, Y., Ito, Y., Nakano, K.: An FPGA implementation for neural networks with the FDFM processor core approach. Int. J. Parallel Emergent Distrib. Syst. 28(4), 308–320 (2013)

2. Bordim, J.L., Ito, Y., Nakano, K.: Accelerating the CKY parsing using FPGAs. IEICE Trans. Inf. Syst. E86–D(5), 803–810 (2003)

3. Cormen, T.H., Leiserson, C.E., Rivest, R.L., Stein, C.: Introduction to Algorithms. MIT Press, Cambridge (2001)

4. Devi, R., Singh, J., Singh, M.: VHDL implementation of GCD processor with built in self test feature. Int. J. Comput. Appl. 25(2), 50–54 (2013)

5. Fujimoto, N.: High throughput multiple-precision GCD on the CUDA architecture. In: Proceedings of the International Symposium on Signal Processing and Information Technology, pp. 507–512, December 2009

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