Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting-Reference-Cited by-同舟云学术

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting

Published:2016 Issue: Volume: Page:277-289
ISSN:0302-9743
Container-title:Architecture of Computing Systems – ARCS 2016
language:
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Author:

Marcu Marius,Boncalo Oana,Ghenea Madalin,Amaricai Alexandru,Weinstock Jan,Leupers Rainer,Wang Zheng,Georgakoudis Giorgis,Nikolopoulos Dimitrios S.,Cernazanu-Glavan Cosmin,Bara Lucian,Ionascu Marian

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-30695-7_21

Reference15 articles.

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2. Bouajila, A., Lakhtel, A., Zeppenfeld, J., Stechele, W., Herkersdorf, A.: A low-overhead monitoring ring interconnect for MPSoC parameter optimization. In: Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2012), Tallinn, Estonia, April 2012

3. Madduri, S., Vadlamani, R., Burleson, W., Tessier, R.: A monitor interconnect and support subsystem for multicore processors. In: Proceedings of Design, Automation & Test Europe (DATE 2009) Nice, France, April 2009

4. Zhao, J., Madduri, S., Vadlamani, R., Burleson, W., Tessier, R.: A dedicated monitoring infrastructure for multicore processors. IEEE Trans. VLSI Syst. 19(6), 1011–1022 (2011)

5. Choi, S., Hwang, H., Song, B., Cha, H.: Hardware-assisted energy monitoring architecture for micro sensor nodes. J. Syst. Arch. 58(2), 73–85 (2012)

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