Reducing NoC and Memory Contention for Manycores-Reference-Cited by-同舟云学术

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Reducing NoC and Memory Contention for Manycores

Published:2016 Issue: Volume: Page:293-305
ISSN:0302-9743
Container-title:Architecture of Computing Systems – ARCS 2016
language:
Short-container-title:

Author:

Chandru Vishwanathan,Mueller Frank

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-30695-7_22

Reference31 articles.

1. Wulf, W.A., McKee, S.A.: Hitting the memory wall: implications of the obvious. ACM SIGARCH Comput. Archit. News 23(1), 20–24 (1995)

2. Programming The Tile Processor, Tilera. http://www.tilera.com/

3. Application Libraries Reference Manual, Tilera. http://www.tilera.com/

4. Tilera processor family. www.tilera.com

5. Intel xeon phi, April 2015. https://www-ssl.intel.com/content/www/us/en/processors/xeon/xeon-phi-coprocessor-datasheet.html

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1. A shared libraries aware and bank partitioning-based mechanism for multicore architecture;Soft Computing;2023-04-24

2. Reliable Reverse Engineering of Intel DRAM Addressing Using Performance Counters;2020 28th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS);2020-11-17

3. Understanding the performance of storage class memory file systems in the NUMA architecture;Cluster Computing;2018-07-24

4. Minimising Access Conflicts on Shared Multi-Bank Memory;ACM Transactions on Embedded Computing Systems;2017-10-10

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