A Framework for Network-On-Chip Comparison Based on OpenSPARC T2 Processor
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-20227-3_13
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3. Quaglio, F., Vacca, F., Castellano, C., Tarable, A., Masera, G.: Interconnection framework for high-throughput, flexible ldpc decoders. In: Proceedings Design, Automation and Test in Europe (DATE), vol 2. (2006)
4. Condo, C., Martina, M., Masera, G.: Vlsi implementation of a multi-mode turbo/ldpc decoder architecture. IEEE Trans. Circuits Syst. 60(I), 1441–1454 (2013)
5. Tota, S., Casu, M., Ruo Roch, M., Rostagno, L., Zamboni, M.: Medea: a hybrid shared-memory/message-passing multiprocessor noc-based architecture. In: Design, Automation Test in Europe Conference Exhibition (DATE) pp. 45–50 (2010)
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