High Speed VLSI Architecture for Finding the First W Maximum/Minimum Values-Reference-Cited by-同舟云学术

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High Speed VLSI Architecture for Finding the First W Maximum/Minimum Values

Published:2015-08-08 Issue: Volume: Page:35-41
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
Short-container-title:

Author:

Xiao Guoping,Ahmad Waqar,Zaidi Syed Azhar Ali,Roch Massimo Ruo,Causapruno Giovanni

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-20227-3_5

Reference10 articles.

1. Papaharalabos, S., Mathiopoulos, P.T., Masera, G., Martina, M.: Novel non-recursive max* operator with reduced implementation complexity for turbo decoding. IET Commun. 6(7), 702–707 (2012)

2. Leroux, C., Jego, C., Adder, P., Jezequel, M., Gupta, D.: A highly parallel turbo product code decoder without interleaving resource, In: IEEE Workshop on Signal Processing Systems, pp. 1–6 (2008)

3. Condo, C., Martina, M., Masera, G.: VLSI implementation of a multi-mode turbo/LDPC decoder architecture. IEEE Trans. Circuits Syst. I 60(6), 1441–1454 (2013)

4. Boutillon, E., Conde-Canencia, L.: Bubble check: a simplified algorithm for elementary check node processing in extended min-sum non-binary LDPC decoders. IET Electron. Lett. 46(9), 633–634 (2010)

5. Zhang, X., Cai, F.: Reduced-complexity decoder architecture for non-binary LDPC codes. IEEE Trans. VLSI 19(7), 1229–1238 (2011)

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