Eliminating Static Analysis False Positives Using Loop Abstraction and Bounded Model Checking-Reference-Cited by-同舟云学术

Eliminating Static Analysis False Positives Using Loop Abstraction and Bounded Model Checking

Published:2015 Issue: Volume: Page:573-576
ISSN:0302-9743
Container-title:FM 2015: Formal Methods
language:
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Author:

Chimdyalwar Bharti,Darke Priyanka,Chavda Anooj,Vaghani Sagar,Chauhan Avriti

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-19249-9_35

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4. Darke, P., Chimdyalwar, B., Venkatesh, R., Shrotri, U., Metta, R.: Over-approximating loops to prove properties using bounded model checking. In: DATE (2015)

5. Ganai, M., Gupta, A., Ivani, F., Kahlon, V., Li, W., Papakonstantinou, N., Sankaranarayanan, S., Wang, C.: Towards precise and scalable verification of embedded software. In: DVCon (2008)

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