1. E. Best, R. Devillers, Synthesis and reengineering of persistent systems. Acta Inform. 52(l), 35–60 (2015)
2. R. Brayton, L.P. Carloni, A.L. Sangiovanni-Vincentelli, T. Villa, Design automation of electronic systems: past accomplishments and challenges ahead. Proc. IEEE 103(11), 1952–1957 (2015).
3. R. Clarisó, J. Cortadella, Verification of timed circuits with symbolic delays, in Proc. of Asia and South Pacific Design Automation Conference, January (2004), pp. 628–633
4. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev, Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans. Inf. Syst. E80-D(3), 315–325 (1997)
5. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev. Logic Synthesis of Asynchronous Controllers and Interfaces (Springer, Berlin, 2002)