1. Adams, R. D. High performance memory testing: design principles, fault modeling and self-test. Kluwer Academic Publishers, USA, 2003.
2. Banerjee, S., Mukhopadhyay, D., and Chowdhury, D. R. Automatic generated built-in-self-test for embedded memory. In Proceedings of the IEEE First India Annual Conference (Dec. 2004), INDICON’04., pp. 377–380.
3. Barzilai, Z., Coppersmith, D., and Rozenberg, A. Exhaustive generation of bit pattern with application to VLSI self-testing. IEEE Transactions on Computers c-31, 2 (1983), 190–194.
4. Bernardi, P., Grosso, M., Reorda, M. S., and Zhang, Y. A programmable bist for dram testing and diagnosis. In Proceedings of the IEEE International Test Conference (Nov. 2010), ITC’10, pp. 1–10.
5. Cascaval, P., Bennett, S., and Huţanu, C. Efficient march tests for a reduced 3-coupling and 4-coupling faults in random-access memories. Journal of Electronic Testing 20, 3 (2004), 227–243.