A Fault Injection System for Measuring Soft Processor Design Sensitivity on Virtex-5 FPGAs
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-14352-1_5
Reference18 articles.
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3. Mansour W, Velazco R (2013) An automated SEU fault-injection method and tool for HDL-based designs. IEEE Trans Nucl Sci 60(4):2728–2733. doi: 10.1109/TNS.2013.2267097
4. Nazar G, Carro L (2012) Fast single-FPGA fault injection platform. In: Defect and fault tolerance in VLSI and nanotechnology systems (DFT), 2012 IEEE international symposium on, pp 152–157. doi: 10.1109/DFT.2012.6378216
5. Lima F, Carmichael C, Fabula J, Padovani R, Reis R (2001) A fault injection analysis of Virtex FPGA TMR design methodology. In: 6th European conference on radiation and Its effects on components and systems, IEEE (2001), pp 275–282. doi: 10.1109/RADECS.2001.1159293
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