Statistical Reliability/Energy Characterization in STT-RAM Cell Designs
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-15180-9_7
Reference31 articles.
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5. Y. Chen, W.-F. Wong, H. Li, C.-K. Koh, Y. Zhang, W. Wen, On chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. J. Emerg. Technol. Comput. Syst. 9(2), 16:1–16:22 (2013)
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