10 Bit 1.5b/Stage Pipeline ADC Design for Video Application
Author:
Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-319-04573-3_75
Reference10 articles.
1. Sall, E., Vesterbacka, M., & Andersson, K. O. (2004). A study of digital decoders in flash analog to digital converters. IEEE International Symposium on Circuits System, Vancouver, Canada.
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3. Cho, S. H., Lee, C. K., Lee, S. G., & Ryu, S. T. (2010). A two-channel asynchronous SAR ADC with metastable-then-set algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), 765–769.
4. Signore, B. P., Kerth, D. A., Sooch, N., & Swanson, E. (1990). A monolithic 20-b delta-sigma A/D converter. IEEE Journal of Solid-State Circuits, 25, 1311–1317.
5. Mahajan, D., Kakkar, V., & Singh, A. K. (2011). Analysis of delta sigma modulator. 2011 International Conference on Computational Intelligence and Communication Networks (CICN) (pp. 182–186).
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