Formal Verification of SystemC-based Cyber Components-Reference-Cited by-同舟云学术

Formal Verification of SystemC-based Cyber Components

Published:2016-10-13 Issue: Volume: Page:137-167
ISSN:2365-4139
Container-title:Industrial Internet of Things
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Author:

Große Daniel,Le Hoang M.,Drechsler Rolf

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-42559-7_6

Reference34 articles.

1. Große D, Le HM, Drechsler R (2010) Proving transaction and system-level properties of untimed SystemC TLM designs. In: ACM and IEEE international conference on formal methods and models for codesign, pp 113–122

2. Bailey B, Martin G, Piziali A (2007) ESL design and verification: a prescription for electronic system level methodology. Morgan Kaufmann, Amsterdam

3. IEEE Standard for Standard SystemC Language Reference Manual (2012) IEEE Std. 1666

4. Pasricha S (2002) Transaction level modeling of SoC with SystemC 2.0. In: SNUG

5. Cai L, Gajski D (2003) Transaction level modeling: an overview. In: IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, pp 19–24

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