Publisher
Springer International Publishing
Reference16 articles.
1. Carter, T.M., Robertson, J.E.: The set theory of arithmetic decomposition. IEEE Trans. Comput. 39, 993–1005 (1990)
2. Avizienis, A.A. Signed-digit number representations for fast parallel arithmetic. IRE Trans. Electron. Comput. 10(3), 389–400 (1961)
3. Chow, C.Y., Robertson, J.E.: Logical design of a redundant binary adder. In: Proceedings of the 4th Symposium on Computer Arithmetic, pp. 109–115 (1978)
4. Zehendner, E.: Reguläre parallele Addierer für redundante binäre Zahlsysteme. Technical Report, Report 255, Institut für Mathematik der University ät Augsburg (1992)
5. Alioto, M., Palumbo, G.: Analysis and comparison on full adder block in submicron technology. IEEE Trans. Very Large Scale Integr. VLSI Syst. 10(6), 806–823 (2002)