1. Bromley J (2013) If systemverilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language. In: 2013 Forum on Specification & Design Languages (FDL), IEEE, Paris
2. Oliveira FS, Haedicke F, Drechsler R, Kuznik C, Le HM, Ecker W, Mueller W, Große D, Esen V (2012) The system verification methodology for advanced TLM verification. In: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, ACM, New York, pp 313–322
3. Zhaohui H, Pierres A, Shiqing H, Fang C, Royannez P, See EP, Hoon YL (2012) Practical and efficient SOC verification flow by reusing IP testcase and testbench. In: 2012 International SoC Design Conference (ISOCC), IEEE, Jeju Island, pp 175–178
4. Raghuvanshi S, Singh V (2014) Review on universal verification methodology (UVM) concepts for functional verification. Int J Electr Electron Data Commun 2(3):101–107
5. Young-Nam Yun (2011) Beyond UVM for practical SoC verification. In: International SoC design conference (ISOCC), IEEE, Jeju, pp 158–162