Background and Related Work
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-77479-4_2
Reference48 articles.
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2. Kultursay, E., Swaminathan, K., Saripalli, V., Narayanan, V., Kandemir, M.T., Datta, S.: Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores. In: Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 245–254 (2012)
3. Raghunathan, B., Garg, S.: Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era. In: Proceedings of the 9th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (2014)
4. Ebi, T., Al Faruque, M.A., Henkel, J.: TAPE: Thermal-aware agent-based power economy for multi/many-core architectures. In: the International Conference on Computer-Aided Design (ICCAD), pp. 302–309 (2009). https://doi.org/10.1145/1687399.1687457
5. Sartori, J., Kumar, R.: Three scalable approaches to improving many-core throughput for a given peak power budget. In: Proceedings of the International Conference on High Performance Computing (HiPC), pp. 89–98 (2009)
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