1. M.S. Arthur, H. M. Roermund, Herman Casier, Analog circuit design, (Springer, Netherlands, 2010)
2. B. Brannon, Sampled systems and the effects of clock phase noise and jitter. Analog Devices Appl. Note, (2004)
3. H. Wu, Y.P. Xu, A 1v 2.3 $$\mu $$ μ w biomedical signal acquisition ic, in Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International (Feb 2006), pp. 119–128
4. W. Liu, P. Huang, Y. Chiu, A 12-bit, 45-ms/s, 3-mw redundant successive-approximation-register analog-to-digital converter with digital calibration. Solid-State Circuits, IEEE J. 46, 2661–2672 (2011)
5. J. Fredenburg, M. Flynn, Statistical analysis of enob and yield in binary weighted adcs and dacs with random element mismatch. Circuits Syst. I: Regul. Pap., IEEE Trans. 59, 1396–1408 (2012)