Author:
Bhat Balasubramanya,Mueller Frank
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Control and Optimization,Computer Networks and Communications,Computer Science Applications,Modeling and Simulation,Control and Systems Engineering
Reference29 articles.
1. Akesson B, Goossens K, Ringhofer M (2007) Predator: a predictable SDRAM memory controller. In: CODES + ISSS’07: Proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis. ACM, New York, pp 251–256
2. Atanassov P, Puschner P (2001) Impact of dram refresh on the execution time of real-time tasks. In: Proc IEEE international workshop on application of reliable computing and communication, pp 29–34
3. Ferdinand C, Wilhelm R (1999) Efficient and precise cache behavior prediction for real-time systems. Real-Time Syst 17(2/3):131–181
4. Ghosh M, Lee H-HS (2007) Smart refresh: an enhanced memory controller design for reducing energy in conventional and 3d die-stacked drams. In: MICRO, pp 134–145
5. Hellebrand S, Wunderlich H-J, Ivaniuk AA, Klimets YV, Yarmolik VN (1999) Error detecting refreshment for embedded drams. In: VTS, pp 384–390
Cited by
20 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献