BAT: The Bit-Level Analysis Tool-Reference-Cited by-同舟云学术

BAT: The Bit-Level Analysis Tool

Published: Issue: Volume: Page:303-306
ISSN:
Container-title:Computer Aided Verification
language:
Short-container-title:

Author:

Manolios Panagiotis,Srinivasan Sudarshan K.,Vroon Daron

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-73368-3_35.pdf

Reference7 articles.

1. Lecture Notes in Computer Science;B. Dutertre,2006

2. Lecture Notes in Computer Science;P. Jackson,2005

3. Manolios, P., Srinivasan, S.K.: A complete compositional reasoning framework for the efficient verification of pipelined machines. In: ICCAD 2005. International Conference on Computer-Aided Design, pp. 863–870. IEEE Computer Society Press, Los Alamitos (2005)

4. Manolios, P., Srinivasan, S.K., Vroon, D.: Automatic memory reductions for RTL-level verification. In: ICCAD 2006. ACM-IEEE International Conference on Computer Aided Design, ACM, California (2006)

5. Manolios, P., Srinivasan, S.K., Vroon, D.: BAT: The Bit-level Analysis Tool (2006), available from http://www.cc.gatech.edu/~manolios/bat/

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