Applying Logic Synthesis for Speeding Up SAT-Reference-Cited by-同舟云学术

Applying Logic Synthesis for Speeding Up SAT

Published: Issue: Volume: Page:272-286
ISSN:
Container-title:Theory and Applications of Satisfiability Testing – SAT 2007
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Author:

Een Niklas,Mishchenko Alan,Sörensson Niklas

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-72788-0_26.pdf

Reference16 articles.

1. Biere, A.: AIGER (AIGER is a format, library and set of utilities for And-Inverter Graphs (AIGs), http://fmv.jku.at/aiger/

2. Bjesse, P., Boralv, A.: DAG-Aware Circuit Compression For Formal Verification. In: Proc. ICCAD’04 (2004)

3. Chen, D., Cong, J.: DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs. In: ICCAD, pp. 752–759 (2004)

4. Drechsler, R.: Using Synthesis Techniques in SAT Solvers. Technical Report, Intitute of Computer Schience, University of Bremen, Bremen, Germany (2004)

5. Een, N.: http://www.cs.chalmers.se/~een/SAT-2007

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