Design Flow for Efficient FPGA Reconfiguration

Author:

Turner Richard H.,Woods Roger F.

Publisher

Springer Berlin Heidelberg

Reference4 articles.

1. Turner, R.H.: Functionally Diverse Programmable Logic Implementations of Digital Signal Processing Algorithms, PhD Diss., Queen’s University Belfast (2002)

2. Ang, C.N., Turner, R.H., Courtney, T., Woods, R.: Virtex FPGA Implementation of a Polyphase Filter for Sample Rate Conversion. In: 34th Asilomar Conf. on Signals, Syst. and Comp., USA, pp. 365–369. IEEE Comp. Soc., Los Alamitos (2000)

3. Courtney, T., Turner, R.H., Woods, R.: An Investigation of Reconfigurable Multipliers for use in Adaptive Signal Processing. In: IEEE Symp. on FCCM, Napa, USA, May 2000, pp. 341–343 (2000)

4. Shirazi, N., Luk, W., Cheung, P.: Automating Production of Run-Time Reconfigurable Designs. In: Proc. IEEE Symp. on FCCM, USA, pp. 147–156 (1998)

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