Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-540-95948-9_7
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3. Agarwal, K., Sylvester, D., Blaauw, D.: Variational Delay Metrics for Interconnect Timing Analysis. In: Proc. Design Automation Conference, pp. 381–384 (2004)
4. Choi, S.H., Paul, B.C., Roy, K.: Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology. In: Proc. Design Automation Conference, pp. 454–459 (2004)
5. Agarwal, A., Dartu, F., Blaauw, D.: Statistical Gate Delay Model Considering Multiple Input Switching. In: Proc. Design Automation Conference, pp. 658–663 (2004)
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1. Coupling Transition Reduction on On-Chip Buses Using Adaptive Bus Encoding (ABE);Lecture Notes in Electrical Engineering;2023
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