Integrating Formal Verification with Murφ of Distributed Cache Coherence Protocols in FAME Multiprocessor System Design

Author:

Chehaibar Ghassan

Publisher

Springer Berlin Heidelberg

Reference16 articles.

1. Bull NovaScale® servers, http://www.bull.com/novascale/index.html

2. Chehaibar, G., Garavel, H., Mounier, L., Tawbi, N., Zulian, F.: Specification and Verification of the PowerScale Bus Arbitration Protocol: An Industrial Experiment with LOTOS. In: Proc. of FORTE/PSTV 1996, pp. 435–450 (1996)

3. Dill, D.L., Drexler, A.J., Hu, A.J., Yang, C.H.: Protocol Verification as a Hardware Design Aid. In: IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 522–525. IEEE Computer Society, Los Alamitos (1992)

4. FAME Architecture, Statement of Direction, http://www.bull.com/download/whitepapers/fame.pdf

5. Lecture Notes in Computer Science;K. Fisler,1998

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1. Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip;Formal Methods for Industrial Critical Systems;2013

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