Author:
Kuzmanov Georgi,Gaydadjiev Georgi,Vassiliadis Stamatis
Publisher
Springer Berlin Heidelberg
Reference11 articles.
1. Campi, F., Toma, M., Lodi, A., Cappelli, A., Canegallo, R., Guerrieri, R.: VLIW Processor with Reconfigurable Instruction Set for Embedded Applications. In: ISSCC Digest of Technical Papers, February 2003, pp. 250–251 (2003)
2. Gokhale, M., Stone, J.: Napa C: Compiling for a Hybrid RISC/FPGA Architecture. In: Proc. IEEE Symp. on FCCM, pp. 126–135 (1998)
3. Hauck, S., Fry, T., Hosler, M., Kao, J.: The Chimaera Reconfigurable Functional Unit. In: Proc. IEEE Symp. on FCCM, pp. 87–96 (1997)
4. Kuzmanov, G., Gaydadjiev, G.N., Vassiliadis, S.: Loading rm-code: Design considerations. In: Proc. Third Intl. Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2003), pp. 8–11 (2003)
5. Lecture Notes in Computer Science;G. Kuzmanov,2003
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