Author:
Machanick Philip,Patel Zunaid
Publisher
Springer Berlin Heidelberg
Reference30 articles.
1. Alexander, T., Kedem, G.: Distributed prefetch-buffer/cache design for high-performance memory systems. In: Proc. 2nd IEEE Symp. on High- Performance Computer Architecture, San Jose, CA, February 1996, pp. 254–263 (1996)
2. AMD. HyperTransport technology: Simplifying system design [online] (October 2002), http://www.hypertransport.org/docs/26635A_HT_System_Design.pdf
3. Borkenhagen, J.M., Eickemeyer, R.J., Kalla, R.N., Kunkel, S.R.: A multithreaded PowerPC processor for commercial servers. IBM J. Research and Development 44(6), 885–898 (2000)
4. Chen, T., Baer, J.: Reducing memory latency via non-blocking and prefetching caches. In: Proc. 5th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-5), September 1992, pp. 51–61 (1992)
5. Chen, T.-F.: An effective programmable prefetch engine for on-chip caches. In: Proc. 28th Int. Symp. on Microarchitecture (MICRO-28), Ann Arbor, MI, November 29 – December 1, pp. 237–242 (1995)
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