Author:
Knapp Steffen,Paul Wolfgang
Publisher
Springer Berlin Heidelberg
Reference16 articles.
1. AbsInt Angewandte Informatik GmbH. Worst-Case Execution Time Analyzers (December 2006), http://www.absint.com/
2. Beyer, S., et al.: Towards the formal verification of lower system layers in automotive systems. In: Proceedings 23nd IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD 2005), 2–5 October 2005, pp. 317–324. IEEE Computer Society Press, Los Alamitos (2005)
3. Beyer, S.: Putting It All Together: Formal Verification of the VAMP. PhD thesis, Saarland University, Computer Science Department (March 2005)
4. Lecture Notes in Computer Science;S. Beyer,2003
5. Lecture Notes in Computer Science;G.M. Brown,2006
Cited by
11 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献