MLP-Aware Dynamic Cache Partitioning-Reference-Cited by-同舟云学术

MLP-Aware Dynamic Cache Partitioning

Published: Issue: Volume: Page:337-352
ISSN:
Container-title:High Performance Embedded Architectures and Compilers
language:
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Author:

Moreto Miquel,Cazorla Francisco J.,Ramirez Alex,Valero Mateo

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-77560-7_23.pdf

Reference20 articles.

1. Serrano, M.J., Wood, R., Nemirovsky, M.: A study on multistreamed superscalar processors, Technical Report 93-05, University of California Santa Barbara (1993)

2. Tullsen, D.M., Eggers, S.J., Levy, H.M.: Simultaneous multithreading: Maximizing on-chip parallelism. In: ISCA (1995)

3. Hammond, L., Nayfeh, B.A., Olukotun, K.: A single-chip multiprocessor. Computer 30(9), 79–85 (1997)

4. Cazorla, F.J., Ramirez, A., Valero, M., Fernandez, E.: Dynamically controlled resource allocation in SMT processors. In: MICRO (2004)

5. Chiou, D., Jain, P., Devadas, S., Rudolph, L.: Dynamic cache partitioning via columnization. In: Design Automation Conference (2000)

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