Author:
Torres E. F.,Ibañez P.,Viñals V.,Llabería J. M.
Publisher
Springer Berlin Heidelberg
Reference13 articles.
1. Agarwal, V., et al.: Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures. In: Proc. of 27th ISCA, pp. 248–259 (2000)
2. Burger, D.C., Austin, T.M.: The SimpleScalar Tool Set, Version 2.0. UW Madison Computer Science Technical Report #1342 (1997)
3. Limaye, D., Rakvic, R., Shen, J.P.: Parallel Cachelets. In: Proc. 19th ICCD, September 2001, pp. 284–292 (2001)
4. Cho, S., Yew, P., Lee, G.: A High-Bandwidth Memory Pipeline for Wide Issue Processors. IEEE Trans. on Computers 50(7), 709–723 (2001)
5. Kessler, R.E., MacLellan, E.J., Webb, D.A.: The Alpha 21264 Microprocessor Architecture. In: Proc. of ICCD 1998, October 1998, pp. 90–95 (1998)