1. Alba Pinto, C., Mesman, B., van Eijk, K.: Register files constraint satisfaction during scheduling of DSP code. In: Proceedings of the XII Symposium on Integrated Circuits and Systems Design, Los Alamitos, CA, USA, pp. 74–77. IEEE Computer Society Press, Los Alamitos (1999)
2. Bekooij, M., Mesman, B., van Meerbergen, J., Jess, J.A.G.: Constraint analysis for operation assignment in facts. In: Proceedings of the 11st ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing, Utrecht, The Netherlands, November 2000, pp. 229–236. STW Technology Found (2000)
3. Capitanio, A., Dutt, N., Nicolau, A.: Partitioned register files for VLIWs: A preliminary analysis of tradeoffs. SIGMICRO-Newsletter 23(1-2), 292–300 (1992)
4. Coudert, O.: Exact coloring for real-life graphs is easy. In: Proceedings of the 34th Design Automation Conference, pp. 121–126. ACM, New York (1997)
5. Fernandes, M., Llosa, J., Topham, N.: Partitioned schedules for clustered VLIW architecture. In: Proceedings of the 1st Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processors, pp. 130–134. IEEE Computer Society Press, Los Alamitos (1999)