A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture-Reference-Cited by-同舟云学术

A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture

Published:2007 Issue: Volume: Page:159-170
ISSN:0302-9743
Container-title:Software Technologies for Embedded and Ubiquitous Systems
language:
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Author:

Schlager Martin,Obermaisser Roman,Elmenreich Wilfried

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-75664-4_16

Reference26 articles.

1. Obermaisser, R., Peti, P., Huber, B., El Salloum, C.: DECOS: An integrated time-triggered architecture. e&i journal (Journal of the Austrian professional institution for electrical and information engineering) 3 (March 2006)

2. AUTOSAR GbR. AUTOSAR - Technical Overview V2.0.1 (June 2006)

3. Aeronautical Radio Incorporated (ARINC), Annapolis, MD, USA. ARINC Specification 651: Design Guide for Integrated Modular Avionics (November 1991)

4. National Instruments Corporation. LabVIEW FPGA in hardware-in-the-loop simulation applications (July 2003)

5. Wu, X., Lentijo, S., Deshmuk, A., Monti, A., Ponci, F.: Design and implementation of a power-hardware-in-the-loop interface: a nonlinear load case study. In: Applied Power Electronics Conference and Exposition (APEC) 2005, pp. 1332–1338. IEEE Computer Society Press, Los Alamitos (2005)

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