1. Kim S, Chandra D, Solihin Y. Fair cache sharing and partitioning in a chip multiprocessor architecture. In Proc. the 13th International Conference on Parallel Architectures and Compilation Techniques, September 2004, pp.111-122.
2. Choi I S, Jang S I, Oh C H, Weems C C, Kim S D. A dynamic adaptive converter and management for PRAM-based main memory. Microprocessors and Microsystems, 2013, 37(6/7): 554–561.
3. Jang S I, Yoon S K, Park K, Park G H, Kim S D. Data classification management with its interfacing structure for hybrid SLC/MLC PRAM main memory. The Computer Journal, 2014, DOI 10.1093/comjnl/bxu133.
4. Dhiman G, Ayoub R, Rosing T. PDRAM: A hybrid PRAM and DRAM main memory system. In Proc. the 46th ACM/IEEE Design Automation Conference, July 2009, pp.664-669.
5. Yoon S K, Bian M Y, Kim S D. An integrated memory-disk system with buffering adapter and non-volatile memory. Design Automation for Embedded Systems, 2014, 17(3/4): 609–626.