Author:
Hamaguchi Kiyoharu,Urushihara Hidekazu,Kashiwabara Toshinobu
Publisher
Springer Berlin Heidelberg
Reference17 articles.
1. R. A. Bergamaschi and S. Raje. Observable Time Windows: Verifying The Results of High-Level Synthesis. IEEE Design and Test of Computers, 14(2):40–50, 1997.
2. Lect Notes Comput Sci;R. E. Bryant,1999
3. J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. Symbolic Model Checking for Sequential Circuit Verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(4), April 1994.
4. J. R. Burch and D. L. Dill. Automatic Verification of Pipelined Microprocessor Control. In Proceedings of International Conference on Computer-Aided Design, pages 68–80, June 1994.
5. O. Coudert, C. Berthet, and J.-C. Madre. Verification of Sequential Machines Using Boolean Functional Vectors. In Proceedings of the IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, November 1990.
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