Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
https://link.springer.com/content/pdf/10.1007/s10836-022-06036-5.pdf
Reference22 articles.
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2. Muthu BR, Ewins P, Pushpa VD, Kamala J, Hemalatha V, Oh W-C, Suresh S (2022) “Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell” Sensors 22(1):33. https://doi.org/10.3390/s22010033. Suresh Sagadevan1
3. Bohr MT, Ian A, Young (2017) CMOS Scaling Trends and Beyond. IEEE Micro 37:20–29
4. Kobayashi D (2021) “Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance,“. IEEE Trans Nucl Sci 68(2):124–148. doi: https://doi.org/10.1109/TNS.2020.3044659
5. Moore GE (1965) “Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, pp.114 ff.,“ IEEE Solid-State Circuits Society Newsletter, 11(3):33–35, doi: https://doi.org/10.1109/N-SSC.2006.4785860
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