Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

Author:

Bhunia Swarup,Mahmoodi Hamid,Raychowdhury Arijit,Roy Kaushik

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference24 articles.

1. Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K (2005) Low-power scan design using first-level supply gating. IEEE Trans Very Large Scale Integr Syst 13(3):384–395, Mar

2. Borkar S, et al (2003) Parameter variations and impact on circuits and microarchitecture. Design Automation Conference, pp 338–342

3. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer, Boston

4. Calhoun BH, Honore FA, Chandrakasan A (2003) Design methodology for fine-grained leakage control in MTCMOS. In: International symposium on low power electronics design, Seoul, pp 104–107, 25–27 August

5. Cheng K-T, Devadas S, Keutzer K (1991) A partial en- hanced scan approach to robust delay-fault test generation for sequential circuits. In: International test conference, Nashville, pp 403–410, 26–30 October

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1. The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology;Journal of Low Power Electronics and Applications;2017-04-28

2. A Novel Scan Architecture for Low Power Scan-Based Testing;VLSI Design;2015-04-22

3. Arithmetic module-based built-in self test architecture for two-pattern testing;IET Computers & Digital Techniques;2012

4. Low-Power Design Techniques and Test Implications;Power-Aware Testing and Test Strategies for Low Power Devices;2009-08-13

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