A Single Event Upset Resilient Latch Design with Single Node Upset Immunity
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-019-05823-x.pdf
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5. Buchner S, Warner J, McMorrow D, Miller F, Morand S, Pouget V, Larue C, Adell P, Allen G (2012) Comparison of single event transients generated at four pulsed-laser test facilities-NRL, IMS, EADS, JPL. IEEE Trans Nucl Sci 59(4):988–998
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1. High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets;IEEE Transactions on Aerospace and Electronic Systems;2021-12
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