Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices
Author:
Funder
H2020 Marie Skłodowska-Curie Actions
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
https://link.springer.com/content/pdf/10.1007/s10836-020-05885-2.pdf
Reference30 articles.
1. Akers SB (1972) A rectangular logic array. IEEE Trans Comput C-21(8):848–857. https://doi.org/10.1109/TC.1972.5009040
2. Alexandrescu D, Altun M, Anghel L, Bernasconi A, Ciriani V, Frontini L, Tahoori M (2017) Logic synthesis and testing techniques for switching nano-crossbar arrays. Microprocess Microsyst 54:14–25. https://doi.org/10.1016/j.micpro.2017.08.004
3. Altun M, Riedel MD (2012) Logic synthesis for switching lattices. IEEE Trans Comput 61(11):1588–1600. https://doi.org/10.1109/TC.2011.170
4. Anghel L, Bernaconi A, Ciriani V, Frontini L, Trucco G, Vatajelu I (2019) Fault mitigation of swithcing lattices under stuck-at fault model. In: Proc. of IEEE Latin American test symposium, LATS 2019, Satiago de Chile, March 2019. IEEE
5. Bernasconi A, Ciriani V, Frontini L (2018) Testability of switching lattices in the stuck at fault model. In: Proc. IFIP/IEEE International conference on very large scale integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018. IEEE, pp 213–218
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