A Framework for Configurable Joint-Scan Design-for-Test Architecture
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
https://link.springer.com/content/pdf/10.1007/s10836-021-05978-6.pdf
Reference42 articles.
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2. Adiga R, Arpit G, Singh V, Saluja KK, Singh AD (2010) Modified t-flip-flop based scan cell for RAS. In: Proc. of the European Test Symposium (ETS). IEEE Computer Society
3. Ahlawat S, Tudu J, Matrosova A, Singh V (2018) A high performance scan flip-flop design for serial and mixed mode scan test. IEEE Trans Device Mater Reliab 18(2):321–331. https://doi.org/10.1109/TDMR.2018.2835414
4. Ando H (1980) Testing VLSI with random acecss scan. In: Digest of Computer Society Int. Conference. pp 50–52
5. Baik D, Kajihara S, Saluja K (2004) Random access scan: A solution to test power, test data volume and test time. In: Proc. 17th International Conference on VLSI Design. pp 883–888
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