Author:
Rastogi Ashesh,Ganeshpure Kunal P.,Sanyal Alodeep,Kundu Sandip
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference28 articles.
1. Aloul FA, Hassoun S, Sakallah KA, Blaauw D (2002) Robust SAT-based search algorithm for leakage power reduction. In: Proc Power and Timing Modeling, Optimization and Simulation (PATMOS), pp 167–177
2. ASIC Standard Cell Library Design by Graham Petley, http://www.vlsitechnology.org
3. Bobba S, Hajj IN (1999) Maximum leakage power estimation for CMOS circuits. IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pp 116–124
4. Brown R, Burns J, Devgan A (2003) Efficient techniques for gate leakage estimation. International Symposium on Low Power Electronics and Design (ISLPED), Proceedings, pp 100–103
5. Cao Y, Orhansky M, Sato T, Sylvester D, Hu C et al (2003) Spice up your MOSFET Modeling. IEEE Circuits Devices Mag 19(4):17–23
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