Speed-Up in Test Methods Using Probabilistic Merit Indicators
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-020-05871-8.pdf
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3. Anita JP, Vanathi PT (2014)Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits. In: 2014 International Conference on Electronics and Communication Systems (ICECS), pp 1–6. doi:https://doi.org/10.1109/ECS.2014.6892760
4. Asadi G, Tahoori MB (2005)An analytical approach for soft error rate estimation in digital circuits. In: 2005 IEEE International Symposium on Circuits and Systems, pp 2991–2994 Vol. 2993. doi:https://doi.org/10.1109/ISCAS.2005.1465256
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