Author:
Sun Haijun,Zeng Yongjia,Li Pu,Lei Shaochong,Shao Zhibiao
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference34 articles.
1. Abramovici M, Breuer M, Freidman A (1990) Digital systems testing and testable design. Wiley-Interscience Publication.
2. Abu-Issa AS, Quigley SF (2009) Bit-swapping LFSR and scan-chain ordering: a novel technique for peak-and average-power reduction in scan-based BIST. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28(5):755–759
3. Basturkmen NZ, Reddy SM, Pomeranz I (Oct. 2002) Pseudo random patterns using Markov sources for scan BIST. In Proc. IEEE Test Symp., pp 1013–1021.
4. Bellos M, Bakalis D, Nikolos D (Feb. 2004) Scan cell ordering for low power BIST. In Proc. IEEE Computer society Annual Symp., pp 281–284.
5. Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K (2005) Low-power scan design using first-level supply gating. IEEE Transactions on Very Large Scale Integration Systems 13(3):384–395
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献