Mapping dynamic programming onto modular linear systolic arrays

Author:

Myoupo Jean Frédéric

Publisher

Springer Science and Business Media LLC

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science

Reference32 articles.

1. Benaini A, Tchuente M: Matrix product on linear systolic Arrays. In: Cosnard M, Quinton P, Raynal M, Robert Y (eds) Parallel and distributed algorithms. North Holland 1989

2. Benaini A, Robert Y: A modular systolic linear array for Gaussian Elimination. Int J Comput Math 36:105–118 (1990)

3. Chen MC: A design methodology for synthesizing parallel algorithms and architectures. J Parallel Distrib Comput 3:461–491 (1986)

4. Delosme JM, Ispen ICF: An illustration of a methodology for the construction of efficient systolic architectures. VLSI Int Symp on VLSI Technology, Systems and Applications. Taipei Taiwan 1985, pp 268–273

5. Fisher AL, Kung HT: Synchronizing large VLSI processor arrays. Proc Tenth Ann IEEE/ACM Symp Comput Architec 1983 pp 54–58

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