A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol-Reference-Cited by-同舟云学术

A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol

Published:1994-01 Issue:1 Volume:6 Page:60-91
ISSN:0934-5043
Container-title:Formal Aspects of Computing
language:en
Short-container-title:Form. Asp. Comput.

Author:

Moore J Strother¹

Affiliation:

1. Computational Logic, Inc., 1717 West Sixth Street, Suite 290, 78703-4776, Austin, Texas, USA

Abstract

Abstract We present a formal model of asynchronous communication between two digital hardware devices. The model takes the form of a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into that consumed by an independently clocked processor, given the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on communications at ISO protocol level 1 (physical level). We use the model to show that an 18-bit/cell biphase mark protocol reliably sends messages of arbitrary length between two processors provided the ratio of the clock rates is within 5% of unity.

Publisher

Association for Computing Machinery (ACM)

Subject

Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/BF01211081.pdf

Reference34 articles.

1. Barringer H.: A Survey of Verification Techniques for Parallel Programs . Springer-Verlag Lecture Notes in Computer Science 191 Berlin 1985.

2. Special issue on system verification;Bevier W.R.;Journal of Automated Reasoning,1989

3. Bevier W.R. and Young W.D.: The proof of correctness of a fault-tolerant circuit design. In Proceedings of the Second International Working Conference on Dependable Computing for Critical Applications pp. 107–114. IFIP February 1991.

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Towards correct and reusable Network-on-Chip architectures;Modeling and Simulation of Computer Networks and Systems;2015

2. Automated verification and refinement for physical-layer protocols;Formal Aspects of Computing;2011-05

3. A Formal Approach to the Verification of Networks on Chip;EURASIP Journal on Embedded Systems;2009

4. Machine-Assisted Parameter Synthesis of the Biphase Mark Protocol Using Event Order Abstraction;Lecture Notes in Computer Science;2009

5. A functional formalization of on chip communications;Formal Aspects of Computing;2008-05