1. F. Bassetti, K. Davis, AND D. Quinlan, Temporal Locality Optimizations for Stencil Operations within Parallel Object—Oriented Scientific Frameworks on Cache-Based Architectures, in Proc. of the International Conf. on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, USA, Oct. 1998, pp. 145–153.
2. R. Berrendorf, PCL — The Performance Counter Library: A Common Interface to Access Hardware Performance Counters on Microprocessors (Version 2.0), Forschungszentrum Juelich GmbH, Germany, http://www.fz-juelich.de/zam/PCL , Sept. 2000.
3. C. Douglas, Caching in With Multigrid Algorithms: Problems in Two Dimensions, Parallel Algorithms and Applications, 9 (1996), pp. 195–204.
4. C. Douglas, J. Hu, M. Kowarschik, U. Rude, AND C. Weiss, Cache Optimization for Structured and Unstructured Grid Multigrid, Electronic Transactions on Numerical Analysis, 10 (2000), pp. 21–40.
5. D. Genius AND S. Lelait, A Case for Array Merging in Memory Hierarchies, in Proceedings of the 9th Workshop on Compilers for Parallel Computers (CPC’01), Edinburgh, Scotland, June 2001.