Author:
Letychevskyi O. O.,Odarushchenko O. M.,Peschanenko V. S.,Kharchenko V. S.,Moskalets V. V.
Publisher
Springer Science and Business Media LLC
Reference17 articles.
1. O. O. Letychevskyi, V. S. Peschanenko, V. S. Kharchenko, V. A. Volkov, and O. M. Odarushchenko, “Modeling method for development of digital system algorithms based on programmable logic devices,” Cybern. Syst. Analysis, Vol. 56, No. 5, 710–717 (2020). https://doi.org/https://doi.org/10.1007/s10559-020-00289-8.
2. G. Booch, J. Rumbaugh, and I. Jacobson, Unified Modeling Language User Guide, Addison-Wesley, Boston (2005).
3. D. R. Coelho, The VHDL Handbook, Springer, Boston (1989).
4. System Verilog Tutorial. URL: www.asic-world.com/systemverilog/tutorial.html.
5. VC Formal. URL: https://www.synopsys.com/verification/static-and-formal-verification/vc-formal.html.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Application of Formal Verification Methods in a Safety-Oriented Software Development Life Cycle;2023 13th International Conference on Dependable Systems, Services and Technologies (DESSERT);2023-10-13
2. Towards Evidence-Based Cybersecurity Assessment of Programmable Systems to Ensure the Protection of Critical IT Infrastructure;2023 IEEE 12th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS);2023-09-07