Author:
Banerjia Sanjeev,Havanki William A.,Conte Thomas M.
Publisher
Springer Berlin Heidelberg
Reference11 articles.
1. G. S. Tjaden and M. J. Flynn, “Detection and parallel execution of independent instructions,” IEEE Trans. Comput., vol. C-19, pp. 889–895, Oct. 1970.
2. J. A. Fisher, “Trace scheduling: A technique for global microcode compaction,” IEEE Trans. Comput., vol. C-30, no. 7, pp. 478–490, July 1981.
3. S. A. Mahlke, Exploiting instruction level parallelism in the presence of branches. PhD thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, 1996.
4. B. L. Deitrich and W. W. Hwu, “Speculative hedge: regulating compile-time speculation against profile variations,” in Proc. 29th Ann. Int'l Symp. on Microarchitecture [11].
5. T. M. Conte and S. W. Sathaye, “Dynamic rescheduling: A technique for object code compatibility in VLIW architectures,” in Proc. 28th Ann. Int'l Symp. on Microarchitecture, (Ann Arbor, MI), Nov. 1995.
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. LUCAS;Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems;2013-06-20
2. Feedback-Based Global Instruction Scheduling for GPGPU Applications;Computational Science and Its Applications – ICCSA 2012;2012
3. Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors;Languages and Compilers for Parallel Computing;2003
4. Improving TriMedia Cache Performance by Profile Guided Code Reordering;Lecture Notes in Computer Science