Author:
Stok Leon,Puri Ruchir,Bhattacharya Subhrajit,Cohn John,Sylvester Dennis,Srivastava Ashish,Kulkarni Sarvesh
Reference35 articles.
1. Albrecht, C., Korte, B., Schietke, J., and Vygen, J., “Cycle Time and Slack Optimization for VLSI-Chips, ” proceedings of the International Conference on Computer-Aided Design, 1999, pp. 232-238.
2. Beeftink, F., Kudva, P., Kung, D., Puri, R., and Stok, L., “Combinatorial cell design for CMOS libraries, ” Integration: the VLSI Journal, vol. 29, 2000, pp. 67-93.
3. Bergamaschi, R. A., et al., “High-level Synthesis in an Industrial Environment, ” IBM Journal of Research and Development, vol. 39, 1995.
4. Bernstein, K., et al., High Speed CMOS Design Styles, Kluwer Academic Publishers, Boston, 1998.
5. Chen, C., Srivastava, A., and Sarrafzadeh, M., “On gate level power optimization using dual-supply voltages, ” IEEE Transactions on VLSI Systems, vol. 9, Oct. 2001, pp. 616-629.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Power Optimization for ASIC Design (Low power ASIC);International Journal of Scientific Research in Science, Engineering and Technology;2014-12-01