3D Fabrication Options for High-Performance CMOS Technology

Author:

Topol Anna W.,Koester Steven J.,La Tulipe Douglas C.,Young Albert M.

Publisher

Springer US

Reference37 articles.

1. Moore G (1965) Cramming more components onto integrated circuits. Electronics 38(8):114–117

2. IBM press release (2007) IBM moves Moore's law into the third-dimension http://www-03.ibm.com/press/us/en/pressrelease/21350.wss

3. Guarini K, Wong, H-SP (2004) Wafer bonding for high performance logic applications. In: Alexe M, Goesele U (eds) Wafer bonding: applications and technology. Springer-Verlag, Berlin, pp 157–160

4. http://www.techsearchinc.com / (2007) In: Through Silicon Via Technology: The Ultimate Market for 3D Interconnect. TechSearch International Report

5. http://www.sematech.org/research/3D /

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